1. Field of the Invention
The present invention relates to a semiconductor device and to a disk drive apparatus, such as a floppy disk drive (FDD), hard disk drive (HDD), PD drive, or CD-ROM (compact disk read-only memory) drive, that employs such a semiconductor device.
2. Description of the Prior Art
As an example of a disk drive apparatus, FIG. 5 shows a block diagram of an FDD (floppy disk drive) apparatus. In this figure, reference numeral 1 represents an interface driver circuit; 2 represents a control circuit; 3 represents a read/write circuit; 4 represents a stepping motor driver circuit; 5 represents a spindle motor driver circuit; 6 represents a read/write head; 7 represents an erase head; 8 represents a stepping motor; 9 represents a spindle motor; 10 represents an index sensor; 11 represents a track sensor; and 100 represents an external host apparatus such as a personal computer. Of these elements, the interface driver circuit 1, control circuit 2, read/write circuit 3, and stepping motor driver circuit 4 are formed on a single-chip IC (semiconductor integrated circuit).
Having the above-noted elements, the FDD apparatus operates as follows. The interface driver circuit 1 serves to adjust the data format and the data transfer method between, on the one hand, the data exchanged between the host apparatus 100 and the control circuit 2, and, on the other hand, the data exchanged between the host apparatus 100 and the read/write circuit 3, i.e. the data that is going to be written to or has just been read from a magnetic disk (not shown).
The control circuit 2 receives data from the host apparatus 100 through the interface driver circuit 1, and, in accordance with that data, controls the writing and reading of the data to and from the magnetic disk (not shown). In return, the control circuit 2 feeds data indicating the operating condition of the FDD apparatus to the host apparatus 100 through the interface driver circuit 1.
Under the control of the control circuit 2, the read/write circuit 3, during data writing, feeds the coils of the read/write head 6 (used to write and read data to and from the magnetic disk) and of the erase head 7 (used to erase data from the magnetic disk) with electric currents in accordance with the data fed from the host apparatus 100 through the interface driver circuit 1, and thereby writes the data to the magnetic disk. On the other hand, during data reading, the read/write circuit 3, on the basis of the voltage that appears in the coil of the read/write head 6 in accordance with the data recorded on the magnetic disk, reads the data from the magnetic disk, and feeds the obtained data to the host apparatus 100 through the interface driver circuit 1.
The stepping motor driver circuit 4, under the control of the control circuit 2, drives the stepping motor 8 to transport the read/write head 6 and the erase head 7 radially across the magnetic disk. The spindle motor driver circuit 5, under the control of the control circuit 2, drives the spindle motor 9 to rotate the magnetic disk.
The index sensor 10 enables the control circuit 2 to detect whether the magnetic disk is rotating normally or not, and the track sensor 11 enables the control circuit 2 to detect whether the read/write head 6 and the erase head 7 are positioned at the outermost edge of the magnetic disk or not.
According to a conventional circuit design, the first stage of the input section of the interface driver circuit 1 is configured as shown in FIG. 6. Specifically, a P-channel MOSFET (metal-oxide semiconductor field-effect transistor) (hereafter referred to simply as a “PMOS transistor”) Q1 and an N-channel MOSFET (hereafter referred to simply as an “NMOS transistor”) Q2 constitute an inverter, and the input terminal I of this inverter is connected simultaneously to a pad P, to the node between a pull-up resistor R1 and a pull-down resistor R2 that are connected in series between the supply voltage VCC and the reference potential GND, and also to the node between two protection diodes Di1 and Di2 that are connected in series between the supply voltage VCC and the reference potential GND so as to be each reverse-biased. This circuit is formed within the IC (i.e. to the left of the broken line H).
Moreover, the threshold voltage of the inverter is set to be approximately equal to VCC/2. As a result, when a low level is fed to the pad P, making the input of the inverter lower than VCC/2, then the PMOS transistor Q1 is turned on, and the NMOS transistor Q2 is turned off, and thus the inverter outputs a high level (VCC); by contrast, when a high level is fed to the pad P, making the input of the inverter higher than VCC/2, then the PMOS transistor Q1 is turned off, and the NMOS transistor Q2 is turned on, and thus the inverter outputs a low level (ground level). The reason that the threshold voltage of the inverter is set to be approximately equal to VCC/2, which is the middle value of the supply voltage VCC, is that the threshold voltage should preferably be set to be approximately equal to the middle level between the high and low level fed to the pad P.
Here, note that the output section of the interface driver circuit 1, and also the stepping motor driver circuit 4, includes a circuit that handles a large current (such a circuit will hereafter be referred to as a “large-current driver”). Since such large-current drivers are formed on the same single chip as the input sections of corresponding or other circuits, they tend to cause undesirable phenomena as described below. One example is the variation of the supply voltage VCC that is caused every time a large-current driver is turned on or off. Another example is the voltage drop caused across the resistor R1 by the current (hereafter referred to as the “parasitic current”), indicated by K in FIG. 6, that flows through the resistor R1 and then through the diode Di2 as the result of an NPN-type parasitic transistor T2 being turned on when the level at the collector of an NPN transistor T1 included in a large-current driver drops below the ground level under the influence of the back electromotive force occurring in the motor driven by the large-current driver. The parasitic transistor 72 is, for example, so formed as to have its emitter at the collector of the above-mentioned NPN transistor T1 of the large-current driver, have its base at the P-type substrate connected to the ground level, and have its collector at the cathode of the protection diode Di2 of the input section. When either of these phenomena is present, the voltage fed to the inverter is lower than when none of them is present, even if the voltage that is fed to the pad P through a predetermined impedance is kept constant (such a drop in the voltage fed to the inverter will hereafter be referred to as an “input drop”).
Inconveniently, according to the conventional configuration of the input section, if such an input drop occurs while the pad P is receiving a high level that is only slightly higher than the threshold voltage of the inverter, the level at the input of the inverter is very likely to drop below the threshold voltage, causing the PMOS transistor Q1 to be turned on, and thus causing the inverter to output a high level. This may lead to malfunctioning of the FDD apparatus as a whole.
Moreover, the nearer the input section is placed to the large-current driver, the larger the input drop. Accordingly, to prevent malfunctioning of the FDD apparatus as a whole, the layout within the IC chip needs to be worked out with strict restrictions so that input sections will not be placed adjacent to large-current drivers. This inevitably requires a larger chip area, and thus leads to an undesirable increase in the IC chip size as well as in its cost.